1. Field of the Invention
The invention is directed to a semiconductor component with a semiconductor body having two principal faces, at least two electrodes, at least one electrode being provided on a principal face. The component has zones of mutually opposite conductivity type that are arranged in alternation in the semiconductor body and extend perpendicularly to the two principal faces. When voltage is applied to the two electrodes, the zones arranged in alternation are mutually cleared of charge carriers, so that an essentially constant field strength is built up in the semiconductor body between the two electrodes.
2. Description of the Related Art
German patent DE 43 09 764 discloses a similar semiconductor component. This publication, discloses a power MOSFET with a semiconductor body having an inner zone of the first conductivity type, having a base zone of the second conductivity type that adjoins the inner zone and a first principal face of the semiconductor body and into which a source zone is embedded, and having a drain zone adjoining one of the principal faces of the semiconductor body. Additional zones of the second conductivity type and further additional zones of the first conductivity type that lie between the additional zones of the second conductivity type and that are more highly doped than the inner zone are provided in the inner zone.
As a result of the xe2x80x9cjunction-trenchxe2x80x9d principle realized in this power MOSFET, the name of this principle being based on the generation of the additional zones by trenches, the specific turn-on resistance of highly inhibiting DMOS transistors can be substantially improved: the drift zone that is otherwise uniformly doped in DMOS transistors, is replaced by the alternately arranged zones of mutually opposite conductivity type, i.e., by n-doped zones and p-doped zones arranged in alternation. These n-doped zones and p-doped zones already mutually clear their charge carriers for small voltages applied to the respective electrodes, so that, similar to a PIN diode, a nearly constant field strength between the two electrodes, i.e., the drain electrode or, respectively, the highly doped n+ drain terminal and the source electrode or, respectively, the p-conductive semiconductor body can build up in such a DMOS transistor when an inhibit voltage is applied. The n-doped zones can thereby be more highly doped by about one order of magnitude, which leads to a corresponding reduction of the turn-on resistance.
The above-described principle of clearing the drift region of charge carriers is also applied in lateral resurf (reduced surface field transistors), as described in an article xe2x80x9c1200 V High-Side Lateral MOSFET in Junction-Isolated Power IC Technology Using Two Field-Reduction Layersxe2x80x9d, by J. S. Ajit, Dan Kinzer and Niraj Ranjan in xe2x80x9cInternational Rectifierxe2x80x9d, 233 Kansas Street, El Segundo, Calif. 90245, pages 230-235. Such lateral resurf transistors can be more simply manufactured than vertical structures with zones of different conductivity type in alternation. The lateral format, however, causes a substantially greater area requirement that is greater by a factor of approximately 10 than that given vertical structures.
Various paths are currently taken for manufacturing zones of alternatingly changing conductivity type extending vertically to the principal faces of a semiconductor body, i.e., n-doped zones and p-doped zones: in a first method, build-up technique is employed in which the n-doped zones and the p-doped zones are xe2x80x9cbuilt upxe2x80x9d step-by-step with the assistance of corresponding masks. A second method that is currently under much discussion comprises etching deep trenches or, respectively, holes in, for example, an n-doped semiconductor body and epitaxially filling the holes that have thus arisen with oppositely doped semiconductor material, preferably silicon. For voltages on the order of magnitude of 600 V, the trenches or, respectively, holes must be introduced approximately 40 xcexcm deep and should comprise a depth that does not significantly fall below 2 xcexcm.
This second method allows significantly smaller grids and, thus, smaller turn-on resistances to be realized than with the build-up technique. The filling of the trenches or, respectively, holes, however, presents a great unanswered problem whether or not it will ever be possible to fill the trenches bubble-free. In order to achieve the desired dielectric strength for voltage on the order of magnitude of 600 V, the trenches or, respectively, holes should have a depth of 40 xcexcm. The manufacture of a vertical resurf transistor with the methods being currently developed poses problem when a dielectric strength up to approximately 600 V or more is to be achieved.
German patent DE 19 600 400 A1 discloses a micro-mechanical component with a planarized cover on a cavity. This cover comprises a membrane layer and a cover layer that is preferably composed of doped glass. The cover layer is subjected to a flow step, in which this layer does not flow into the cavity but rather forms a planar cover at an upper or lower edge.
An object of the present invention is to provide a semiconductor component of the species initially cited such that the component can be produced without the problems such as bubbles in trenches, discussed above. An additional object a method for manufacturing such a semiconductor component as well as the advantageous employment of it.
This object is achieved by semiconductor component is provided comprising a semiconductor body with two principal faces, at least two electrodes wherein at least one of the electrodes is provided on one of the principal faces, and zones of a conductivity type opposite one another that are arranged in alternation in the semiconductor body and extend perpendicularly to the two principal faces, an application of a voltage to the two electrodes mutually clearing the zones of charge carriers so that an essentially constant field strength is built up in the semiconductor body between the two electrodes the containing at least one cavity that is closed by a glass layer or by a sputtered layer.
This object is also achieved by a method for manufacturing a semiconductor component, comprising the sequential steps of introducing trenches into a semiconductor body; applying a thin epitaxial layer or a doped oxide layer on the inside walls of the trenches, producing a remaining cavity, and closing the remaining cavity of the trenches with a doped glass layer or a sputtered layer.
Advantageous developments of the invention are recited below.
What is critical about the inventive semiconductor component is that it contains at least one cavity that can have a trench structure with a width of, for example, 1 xcexcm and a depth of, for example, 40 xcexcm. This cavity is closed at its end lying opposite the one principal face, to which end a glass layer can be utilized. This glass layer can, for example, be composed of doped borophosphorous silicate (BPSG). Another possibility for closing the cavity is comprised in sputtering a cover layer.
The inside walls of the cavity can be provided with a passivation layer of, for example, silicon dioxide.
What is critical about the inventive semiconductor component is that the complete filling of holes or, respectively, trenches is foregone. On the contrary, the trenches remain after the manufacture of the oppositely doped zones arranged in alternation. This zones can be generated, for example, by etching trenches and subsequent epitaxial deposition or be deposition of a doped oxide onto the inside surface of the trenches and subsequent drive-out from the doped oxide.
The standard etching technique can be utilized for the production of the trenches themselves or, on the other hand, an electrochemical method can be utilized. It is significant, however, that the trenches still have an opening of approximately 1 xcexcm over their entire depth of, for example, 40 xcexcm after the production of the zones that are doped opposite one another.
The inside wall of the trenches is passivated by a thin oxide layer before closing these trenches, a gate oxide layer that, for example, is 50 nm thick may be utilized for this purpose.
The closing of the trenches or, respectively, holes can, for example, be undertaken by deposition of a doped glass such as, for example, borophosphorous silicate glass and subsequent flowing in a vacuum. However, a closure layer can also be applied onto the openings of the trenches or, respectively, holes by sputtering.
After application of the doped glass, this closure layer is wet-chemically etched back in a standard way in diluted hydrofluoric acid (HF), so that a planar surface structure arises.
When a vertical resurf transistor is manufactured, then the transistor structure can be subsequently built up between the trenches with a standard DMOS cell. However, it is also possible, for example, to produce a DMOS transistor first and to subsequently etch the trenches or, respectively, holes and to thenxe2x80x94explained above, dope and close these.